A Novel Power and Area Efficient Bidirectional Shift Register Design using Single Phase Clock based Master Slave Flip-Flop

This manuscript presents a brief idea for the implementation of a novel 3-bit bi-directional shift register. The proposed shift register exploits a new single-phase clock-based master slave flip-flop (Proposed_MS) and presents a unique mode selection circuitry to perform shift operation (right/left). The Proposed_MS offers the rewards of low leakage and reduced clock load as compared to NMOS Pass master slave flip-flop (NMOS Pass_MS). Further, the new mode selection circuit uses only 4 transistors which utilize 350% less area as compared to conventional mode selection circuit. Hence, the proposed 3-bit bidirectional shift register (Proposed_MS_SR) saves area overhead as compared to conventional 3-bit bidirectional shift register (Conventional_MS_SR). The Proposed_MS consumed 88.66 µW of power with 1.2V supply voltage which is 29.56% less than the power consumed by NMOS Pass_MS. The delay offered by the proposed circuitry reduces by 50.029 % as compared to conventional shift register. The overall work was carried out at 90nm technology on Cadence at 1.2V supply voltage.