High-Performance Computing with FPGA-Based Parallel Data Processing Systems

Traditional architectures of Central Processing Units (CPUs) and Graphics Processing Units (GPUs) are becoming unsuitable for High-Performance Computing (HPC) due to their high-power consumption and inability to process data in real-time. This study proposes a novel parallel data processing system that is based on FPGAs and capitalizes on the remarkable reconfigurability of FPGAs to enhance the speed and efficiency of computation. The system's modular architecture combines pipeline parallelism with dataflow computation, enabling the continuous and concurrent execution of tasks with a substantially reduced latency. Throughput and scalability are enhanced by dynamic task scheduling, enhanced resource allocation, hardware-accelerated compute cores, and other critical features. The proposed FPGA-based system boasts a throughput that is up to five times greater, a latency that is 60% lower, and a power consumption that is 40% lower than conventional architectures based on CPUs and GPUs, as evidenced by the results of their experiments.