Design Optimization of a 3.3 V Bus Converter for Vertical Power Delivery in Next-Generation Processors

The advancements in artificial intelligence and machine learning are driving the development of a new generation of ultra-powerful graphical processing units (GPUs). The latest datacenter-grade GPU cards use the two-stage lateral power delivery with a traditional 12V intermediate bus voltage (IBV). The next-generation GPUs are expected to double in power and package size, resulting in less space for higher power delivery. A previous study proposed a two-stage vertical power delivery solution by relocating the 2^nd stage converters with a lower IBV. In this architecture, an unregulated LLC resonant converter (DCX) based 1^st stage intermediate bus converter (IBC) steps down 48V to a low IBV, and the 2^nd stage is a packaged voltage regulator stacked under the GPU minimizing the power delivery network (PDN) length; however, the I²R losses at a very low IBV will limit the overall high-power delivery. To ensure the high-power delivery to future GPUs, this paper focuses on the design of a high-efficiency, high-density 1^st stage IBC with an IBV of 3.3V. A high-density LLC DCX based unit-cell design is implemented enabling the high-power delivery symmetrically. By optimizing the winding arrangement, the leakage flux and winding ac resistance of the transformer are minimized. Additionally, the non-ideal current sharing associated with the top-cooled module is mitigated. The elimination of these issues is critical as they lead to the degradation of parallel winding effectiveness and a reduction in efficiency. The proposed improvements are verified by developing an 840W 3.3V bus converter prototype with a peak efficiency of 97.3% and a power density of 2300 W/in.