ZVS Operation and Current Ripple Minimization in a Capacitively Blocked Dual Active Half-Bridge Converter

Current power architecture of server motherboards a two-stage architecture involves an initial conversion and a subsequent step-down. The first stage typically converts 48V to 12V using isolated topologies known as intermediate bus converter (IBC). The second stage then steps down the voltage from 12V to 1V using hard-switched Synchronous Buck Converters (SBC). Such an architecture suffers from the requirement of isolated gate drivers, switching losses, EMI emissions, and limited operating switching frequency. These issues can be addressed by a capacitively blocked dual active half-bridge with a soft switching non-isolated topology. The proposed analysis reveals the ZVS operation of all four switches over a wide range of input voltage and load variation. A current ripple minimization technique based on variable frequency modulation is introduced to reduce the rms and peak inductor current which in turn improves the efficiency. SIMPLIS simulation and experimental measurements showcasing ZVS operation and current ripple minimization at different frequencies and operating points are discussed to validate the proposed approach.