Invited Paper: Area Efficient Low Power Data Transmission Circuit with Analog Differential Data Selector for CMOS Image Sensor

This paper presents an area efficient, low power data transmission circuit for CMOS image sensor (CIS). In this circuit, a novel analog $2: 1$ data selector with differential structure has been proposed, which reduces 62% power consumption and 70% layout area comparing with conventional circuits. The data transmission circuit with serializer and LVDS driver has been designed based on $1 \mathrm{P} 6 \mathrm{M} \quad 0.15 \mu \mathrm{~m}$ CMOS process with chip area of $2.31 \mathrm{~mm} \times 1.34 \mathrm{~mm}$, and it achieves a maximum transmission rate of 1.25Gbps with transmission energy efficiency of $2.88 \mathrm{pJ} / \mathrm{bit} / \mathrm{pF}$.