A Comprehensive Study on Low Power Novel 1-Bit CMOS Full Adders: Comparative Analysis and Performance Evaluation

The continuous advancement of low-power 1-bit full adder designs is a critical factor in the development of modern VLSI systems. This paper presents a comprehensive review of recent innovations in full adder circuits, focusing on hybrid logic, FinFET-based architectures, and Gate Diffusion Input (GDI) techniques. These designs aim to optimize key metrics such as power consumption, propagation delay, and area efficiency, addressing the increasing demand for energy-efficient, high-performance VLSI systems. Hybrid logic approaches, which combine CMOS, PTL, and TGL, demonstrate a balanced trade-off between power and area efficiency, while FinFET-based designs offer superior scalability and control over leakage currents at sub-20 nm technology nodes. GDI techniques, though promising in reducing transistor count and power, face challenges related to voltage degradation, requiring further innovation to maintain robust performance. The analysis highlights the trade-offs inherent in these designs and underscores the importance of the power-delay product (PDP) as a key figure of merit. Furthermore, the paper explores future directions in full adder design, including multi-threshold CMOS (MTCMOS), dynamic threshold MOS (DTMOS), and 3D-IC integration, to further enhance power efficiency and scalability in next-generation VLSI applications.