Short Review on Optimization Adapted Reliable Constraints Based DES in VLSI for Power Grid Design

The process of manufacturing VLSI chips is labour-intensive and includes the critical power planning phase, in which the on-chip GN is developed, evaluated, and adjusted to deliver a high-yielding device. Planning power is getting harder as technology becomes advanced. Ensuring that each chip component has adequate power to operate at the proper voltage levels is the primary objective of the power planning procedure. Nevertheless, the resistance of the metallic lines causes some undesirable IR drop, lowering the voltage levels in numerous on-chip circuits. This work is presented to perform a short survey on Design Space Exploration (DSE) in VLSI for power grid design. For performing the survey, we have adopted 20 articles based on DSE in VLSI designs. Here, we make contributions to varied techniques as well as the modelling (2D or 3D modelling) deployed for designing VLSI circuits. In addition, we review the practical constraints adopted in each paper. Moreover, the performance metrics as well as chronological review are analyzed. Finally, research gaps on DSE in VLSI for power grid design are discussed and to be undertaken in future.