Functionally-Equivalent Formalization and Automated Model Checking of Function Block Diagrams

In the development and verification of safety-critical and safety-related Instrumentation and Control (I&C) systems, it is essential to ensure there is no deviation from the requirements of the assignment during development. Model checking is a method of formal verification which can be used to prove whether a formal model satisfies its formal requirement. Since algorithms of I&C systems are generally informal, they can not be verified by model checking directly, but they must be carefully translated. This article presents a new method based on functionally-equivalent formalisation and model checking. This method can be used for automatic verification of I&C algorithms by model checking while preserving obtained proofs from a formalised model in the original algorithm. There are several problems associated with the verification of PLCs by model checking: 1) State space explosion, 2) Model consistency, 3) Specifying Properties to be Checked, 4) Representing PLC execution cycle, 5) TONs timers representation. This aims of this article is to address points 1), 2), 4) and 5). The article also presents conditions for implementing these algorithms in a target I&C system under which the obtained proofs can also be expected in the physical I&C system. This article primarily focuses on formalisation and model checking of Function Block Diagram (FBD) algorithms. However, the presented methods can also be extended to other programming languages.