A study on chip delay measurement sensor based on scan chain

The reliability and performance of integrated circuits degrade over time, with one critical factor being the aging of numerous internal combinational logic circuits. Delay variations in these circuits not only reflect the chip's external environmental conditions but also indicate the degree of aging during its operational life. Traditional aging delay measurement sensors typically employ dedicated sampling circuits, which pose challenges for comprehensive detection of delays across all combinational logic paths within the chip. This study introduces a novel chip aging sensor, termed the FATE-Sensor, which leverages the internal scan chains of the chip. By performing a full-chip frequency scan of the combinational logic circuits, the FATE-Sensor can detect delay variations at various combinational logic locations using the extensive coverage provided by the scan chains. This paper presents a detailed investigation of the FATE-Sensor's characteristics, including its consistency, repeatability, temperature and voltage dependencies, and resolution enhancement. Experimental calibration of the FATE-Sensor demonstrates its effectiveness in monitoring and reflecting delay variations within the chip's internal circuits. This capability allows for accurate assessment of the chip path delay status, thus enhancing the reliability of chips used in high-precision and advanced applications. This technology not only aids in identifying potential faulty chips and supports chip timing verification testing but also provides new insights for understanding and extending chip lifespan.