Lightweight AES Design for IoT Applications: Optimizations in FPGA and ASIC With DFA Countermeasure Strategies

With the increasing interconnectivity of devices, the Internet of Things (IoT) has revolutionized the industry and daily life. However, the proliferation of IoT devices has also increased security risks, which requires robust protection mechanisms for sensitive data and critical infrastructure. The Advanced Encryption Standard (AES) remains the benchmark for securing IoT systems while balancing low power consumption, minimal area usage, and moderate throughput with high security. This paper offers a comprehensive review of the latest lightweight AES architectural designs, including optimizations to the Substitution Box (S-Box), Sub-Bytes, Shift Rows, Mix Columns, and Add Round Key steps, assessing their impact on gate count, area, maximum frequency, power consumption, and throughput in field programable gate arrays (FPGA) and Application-specific integrated circuit (ASIC) implementations. In addition, this study addresses vulnerabilities in lightweight AES cryptographic hardware to side-channel attacks (SCA), specifically focusing on Differential Fault Analysis (DFA). In addition, the analysis explores fault scenarios, rounds, and injection positions to assess the severity of the fault. In addition, the study reviews DFA countermeasures that highlight fault detection methods, error detection levels, protection positions, and associated design overheads such as area, frequency, and throughput penalties, with special consideration for resource-constrained IoT devices. This study identifies critical gaps in lightweight AES and security challenges while discussing countermeasures that balance security with design efficiency. Finally, this study provides valuable insights for finding research directions to strengthen the robustness of AES in lightweight IoT environments.