Performance Analysis of Residual Number System Digital Filter for Software Defined Radio

Multiplier effects on complexity of filter design in software defined radio (SDR) is at the alarming rate. The consequences of these effects are high implementation silicon cost, high surface area being used and slow speed of operation. In order to reduce the complexity, the multiplier must be replaced with adder. In that way, the complexity will drastically reduce to the barest minimum. The aim of this paper is to design and implement Residual Number System (RNS) algorithm in digital filter with the purpose of reducing the complexity as well as computational burden on SDR system. Matla b 2020a and Stratix IV Altera FPGA device were used for the design simulations. The filter order was reduced drastically during the multistage, multi-rate implementation. Also, the unsigned floating point and unsigned fixed point for small modulus and large modulus RNS digital filter were compared using the Altera FPGA test bench. The fixed point RNS filter utilized the same resources as floating point RNS for small moduli set with 19% look up table (LUT) hardware saving. However, there was 20% increment in the clock frequency for fixed point RNS filter in comparison with floating point filter, which indicated that fixed point RNS occupied lesser space compared to floating point and this signified lesser complexity and higher computational speed. For large modulus RNS digital filter, there wass 10% hardware saving in LUT utilization and 6% increase in the frequency clock. Thus, there was silicon area reduction and clock frequency improvement when fixed point RNS was used compared to the floating RNS. Design of low complexity RNS digital filter with fixed point features reduces the complexity of high performance SDR system, improves computational speed as well as lower the power levels.