A 0.036mm2 80Mb/s-to-15.96Gb/s C-PHY and D-PHY Combo Receiver with Background Calibrations in 4nm FinFET

Mobile industry processor interface (MIPI) C-PHY and D-PHY have been widely used in various applications for multiple cameras, dual display, and automotive. Especially, C-PHY interface has been attracting solution to deliver expansive bandwidth due to its 3-level coding gain of 2.28bit/symbol over three-wired trio [1]. The sampling clock at receiver is recovered from the clock-embedded trio signal, thus no additional clock lane is required. However, 3-level transitions induce the additional switching jitter which degrades the eye-openings. Also it causes the clock recovery error that the multiple clock edges occur within 1UI period. To recover only one clock edge in 1 UI period, the transition masking range should be calibrated to be around 0.35 UI [1]. To enhance the interface speed more, it is necessary to reduce the skew among trio and to compensate for channel loss. Compared to C-PHY, D-PHY does not need the complex circuits such as encoder/decoder and clock recovery. So, some products for low data bandwidth prefer to use D-PHY rather than C-PHY. To operate according to various bandwidth requirements with the same hardware, developing a combo-type architecture for C-PHY and D-PHY is necessary. In this work, we develop the $80 \mathrm{Mb} / \mathrm{s}-\mathrm{to}-15.96 \mathrm{~Gb} / \mathrm{s}$ C/D-PHY combo receiver which follows MIPI C-PHY v2.1 and D-PHY v2.5 standard [2]. In addition, this work proposes the background calibrations to correct the deterministic skew among wires and to compensate for frequency dependent terms including C-PHY transition masking range and equalizer.