Low-Energy RISC-V Core in 18nm FD-SOI CMOS for Embedded Edge-Computing

This paper presents the enhancements brought to AsteRISC, a highly modulable RISC- V core. We study the energy impact of the M extension and show that data gating, multiple-cycle constraints and frequency scaling help in reducing by a factor 2 the energy consumption of the resulting M -extended core. The core implementation, done in 18nm FD-SOI technology, has a lower dynamic power than Riscy and a commercialized reference core but also a better energy efficiency. Among the different implementations, the most efficient reached a 1.37µ W energy consumption post Signoff with a 727 CoreMark score at 0.77V.