Cachedia: An Environment for Efficient Cache Verification With Graphic Visualization for Debugging

The recent boom in open-source processor architectures such as RISC-V has increased the never-ending demand for peripherals and System-on-Chip (SoC) hardware. With this in mind, how to provide an efficient graphical interface environment to increase the visibility of this system is an important question, not only for processors but also for internal blocks such as caches. This paper introduces Cachedia as an environment for better visualization and debugging of direct-mapped and set-associative hardware caches using graphical interfaces. Cachedia provides a comprehensive and user-friendly environment for designing, debugging, and verifying these systems for a variety of applications. The tool includes a Graphical User Interface (GUI) that allows the user to not only configure, visualize and understand the behavior of a cache but also to create an abstract model view to verify the provided hardware design. This provides a visual method for learning and understanding the system and the tools for further development and verification. The environment successfully generated a view model for a configurable cache that can be instantiated as a block design in Vivado. In summary, using the graphic visualization blocks in Cachedia can potentially be advantageous for debugging complex hardware designs.