8×8 SRAM Cell Array for Low-Power Applications

Memory cells have now become a subject of research to meet the demands of the future for digital electronics and communication systems. SRAM (Static Random-Access Memory), it is used in various VLSI and chips due to its unique capability to retain data. SRAM remains a major device of data storage due to its sizable storage density, quicker accessing time, and consuming less power. It does not require periodic refreshing, making is the most popular memory cell among VLSI designers. SRAM serves as a storage element in VLSI chips, their large storage density and time small access. The scope of this work is to design a 6 transistor SRAM cell along with a $3\times 8$ Decoder, and finally integrating the analog block along with the digital block to form a mixed signal based $8\mathrm{x}8$ SRAM. Today, Static Random-Access Memory (SRAM) has evolved into a standard memory element of any Application Specific Integrated Circuit (ASIC), System on Chips (SoC), as they are fast, robust, almost universally found on the same die with microcontrollers and microprocessors. This work introduces a detailed implementation of 64-bit SRAM using Cadence virtuoso schematic editor and layout suite in 45-nm technology. SRAM significantly outpaces DRAM (Dynamic RAM), using SRAM to the fullest, there is concept caching the memory, meaning saving data in SRAMs on the first load, subsequently reducing time drastically. SRAM can retain stored information until power supplied. Memory components are particularly significant in present-day computers for storing vast amounts of data. As SRAM is much quicker than DRAM, caching the memory is a feasible choice, saving data in SRAMs on the first load, reducing load times immensely. The key benefits of utilizing SRAM and it's fast switching speed and low power usage. This circuit includes a basic memory element, a lookup table for an FPGA, and so on. As servers are normally turned on all time, SRAMs are often used in server based online applications Because SRAMs are expected to further develop, this work will focus on creating an 8×8-Bit SRAM-based cache memory that will primarily be used for its high performance and low power consumption in comparing to DRAM.