An Agile Verification for Multi-core Processor Off-chip Memory System

Multi-core processors utilize off-chip DDR memory to provide high-bandwidth and large-capacity memory access. The off-chip memory system is crucial to processor chip research and development. Seventy percent of the research and development cycle is the verification time, because DDR memory design parameters and working modes are diverse, the verification is time-consuming and resource-consuming, and its verification often becomes the bottleneck of the entire research and development cycle. This paper presents an agile verification platform for off-chip memory systems for multi-core processors and introduces key technologies for improving the efficiency of agile verification. The proposed verification platform includes high-quality test programs and an optimized verification procedure. The test program uses directed and random tests based on prior knowledge and NSA (The Negative Selection Algorithm, NSA), respectively, and three acceleration strategies are designed for the initialization, debugging, and running phase of the verification procedure. To validate the effectiveness of the self-designed 16-core processor, the RTL code of an actual off-chip memory system is used as the verification object. The experimental results demonstrate that when the random test program case is reduced by 40%, there is a 29% improvement in the functional coverage and a 3 to 20 times improvement in verification efficiency. Additionally, a total of 26 design bugs are discovered across four categories. The verification results clearly indicate that the proposed method enhances verification efficiency and is ideal for full-chip functional test and regression test.