Scrambler Optimization with Reduced Cycles and Speed Enhancement Technique

Optimizing a design is a method to make it efficient in terms of area, power or any desired parameter. Optimization can be done either by the designer or by the tool itself. The purpose of this research is to optimize a scrambler where the design is made cycle efficient, such that the output desired after 16 clock cycles is generated within a single clock and therefore enhances the overall speed of the system. Along with this, the final design is also made programmable such that it will work for any desired input polynomial. Therefore, the complete work done includes the integration of programmability and optimization of the scrambler unit in a cycle efficient way. Instead of sending all the bits serially, a parallel bit stream of length 16-bits is sent to the input of the 16-bit scrambler and this bit stream is further processed according to the polynomial of the scrambler to give the desired output. Further, with the ANDing logic introduced in the design, the design has been made programmable.