Analysis and Comparison of Static and Dynamic Power Dissipation for Various Arbitration Schemes Used in Network on Chip Routers

With the progress of integrated circuit technology, a vast array of intellectual property (IP) cores may now be combined onto a single chip. This makes it harder for the IP cores to communicate with one another. In order to get over this communication barrier, there exists a method known as Network On Chip (NoC). This is an on-chip packet-switched network in which IP cores are linked to the network through interfaces. An integral part of NoC architecture is a router. The major components for a router are FIFO, crossbar, and arbiter. This paper closely looks into the aspects of arbiter. A strong arbiter can manage the contention that arises from multiple masters demanding access at simultaneously, reducing system performance loss despite the multi-master interconnect system's many performance constraints. This work implements the designs of different arbitration techniques implemented in the NoC routers using parametric Verilog HDL and analyzes both the static and dynamic power dissipations and tries to provide solution to reduce the same and thus enhancing the performance overall. The performance of the arbiter designs is evaluated through simulations. The RTL implementation is carried out with parametric Verilog HDL and Xilinx Vivado. The device used for this purpose is XC7Z010ICLG225-1L.