True-Single-Phase-Clock Dual-Edge-Triggering Flip-Flop Based on Low Power Control Technique

This paper proposes a method of low power True-Single-Phase-Clock(TSPC) dual-edge-triggering flip-flop based on low power control technology. The method analyzes the working states of the internal nodes of TSPC structure, combines the low power control technology and the necessary jump conditions of each node, eliminates the redundant switching activity of internal nodes, improves the circuit structure, and has no current competition’s phenomenon. The power consumption and total power delay product are reduced. Compared with the single-transistor clocked dual edge triggering flip-flop(STC-DET) which has the lowest power consumption measured, the simulation results show that the power consumption of the circuit with 28nm technology at 1.2V and 0.6V is reduced by 9.7% and 6.1%. At the same time, the experimental results show: the power consumption and delay of the designed circuit are better than other literatures.