Research on Silicon based multi-layer 2.5D Integration for MOS Switch Modules

Integrated microsystems, owing to their remarkable performance and scalability, have garnered increasing popularity within the realm of high-value electronic equipment. Despite this, a prevailing approach in the integration of power devices continues to involve the use of wire bonding, primarily due to concerns over the thermal and mechanical risks associated with power devices. In this study, we introduce a novel multi-layer 2.5D structure designed to incorporate a double-sided cooling (DSC) packaging technology into silicon-based power device integration. This innovative structure is applied to MOS switch modules, which consist of eight p-type MOSFETs (pMOS) and eight n-type MOSFETs (nMOS). The module’s architecture relies on through silicon vias (TSV), micro bumps, and redistribution Layer (RDL) for device interconnection. The aim of this design is to ensure that the MOS switch module exhibits excellent electrical and thermomechanical performance. Electrical simulation results indicate that the parasitic inductance of the MOS switch module is 0.85nH, and the parasitic resistance is 8.04mΩ, demonstrating significant advantages among power chip integration solutions. To further investigate the thermal mechanical properties and reliability of the proposed structure, we conducted a comparative analysis focusing on thermal management efficiency and reliability under different power losses and temperature conditions. Additionally, the temperature-dependent characteristics of the solder within the structures were analyzed using the Anand viscoplasticity model. Parasitic resistance of the MOS switch module was measured to be 9mΩ by the static test under the conditions of 12V/0.5A, which consistent with the simulation results.