Enhanced ISI Analysis and Fast Circuit Simulation of High-Speed Current-Steering DACs

High-linearity current-steering DACs are critical components in wireless and wireline communication systems, but are notoriously time-consuming to design. Nonlinearity from component mismatches and clock skew can be mitigated with DEM and calibration, but the remaining sources of nonlinearity must be managed by painstaking analog design iteration. Typically, exceedingly long circuit simulations, e.g., each on the order of many days, are required to guide the iteration process, which makes for long design cycles. This paper presents an enhanced analysis of DAC error from component mismatches, clock skew, and inter-symbol interference, and applies the results to enable a new circuit-level simulation technique to quantify nonlinearity that is significantly faster than conventional techniques without sacrificing accuracy. It demonstrates via analysis and simulation examples that the technique enables over an order of magnitude speed increase of circuit-level simulations of high-linearity, high-speed, current-steering DACs.