Improved EMC System Design for Microelectronic Applications

Semiconductor manufacturers continuously provide faster, more cost effective and more highly integrated devices. By the end of the decade, clock frequencies are expected to be in the range of 10 GHz and design dimensions will have been reduced to 45 nm compared with 130 nm today. Chip area and component density will have increased with edge lengths in the range of 40 mm in comparison of 20 mm today. With such changes in performance and complexity, the issues of electromagnetic compatibility and parasitic emissions become ever more significant. In this paper a coherent approach to overcoming these problems at both chip and high-density packaging levels in the frame of the MEDEA+ project called MESDIE (Microelectronic EMC System Design for High Density Interconnect and High Frequency Environment - A509) will be presented. The introduction of new submicron technology and higher packaging density on the subsystem level has led to greater customer demand for high-quality semiconductor devices. Semiconductor manufacturers and their application customers now have to deal with constraints on the chip level to meet electromagnetic compatibility (EMC) requirements of systems and subsystems and are therefore searching for suitable solutions. Due to continuous miniaturisation, higher clock frequencies, faster edge rates and more functionalities, the electromagnetic emission (EME) problem is causing more and more trouble for semiconductor manufacturers in various application areas, such as these in automotive, multimedia, telecommunications and computing facilities. Satisfactory EMC microelectronic system designs that eliminate electromagnetic interference in electronic systems and an appropriate design methodology for integrated circuits (ICs) are crucial. Therefore methods and tools for an improved system design taking into account the boundary conditions and appropriate integration into design processes will be a major challenge for the global electronics industry in this decade. In order to achieve higher performance, microelectronic components and subsystems are moving towards ever increasing miniaturisation. This requires improved functionality of the substrate and high density interconnect (HDI)/high density packaging (HDP), as well as the integration of passive elements, EMC protection devices and optimized interconnect systems. As wiring demands and density increase, high density interconnect structures become an essential requirement for wire ability. This can be handled by either the use of new packaging strategies - such as system in package (SiP). Modelling is an important feature which brings together the semiconductor manufacturers, systems houses and R&D institutes with different backgrounds in technology and design methodologies to develop a common strategy on handling radio-frequency, EMC and susceptibility issues (EMC/RF/SI). The modelling aspects have to be handled on three levels: • electromagnetic emissions of IC • susceptibility at chip level and • new high-density interconnect structures. Therefore new approaches are necessary for modelling and simulation of radiation and susceptibility at chip level and new high density interconnect structures to deal with electromagnetic parasites simultaneously on both chip and high-density packaging levels. In addition, tool environment and design flows, rule development, diagnosis and validation on chip and HDP/HDI levels, as well as testing issues, such as the characterization of chip and HDP/HDI parameters have to be covered. To meet these challenges, the following tasks have to be fulfilled: • close the gap between IC-level design and application in terms of new hierarchical system design approaches and high density interconnect technology • achieve higher performance and more compact electronic equipment in relevant applications, such as automotive, telecommunications and consumer electronics • obtain a design methodology for the information network-based society of the future. Parasitic electromagnetic effects - such as reflections and crosstalk on interconnects, delta-I-noise within the power supply system, the threat of electrostatic discharge and ambient pollution by electromagnetic fields - have to be considered all in the design process together with conventional design constraints.