EMC Design Methodology for Microelectronic Systems

Due to increased clock speeds (10 GHz) and data transfer rates (40 GBit/s) in the entire microelectronics area (partly also MEMS) arises an increasing demand for the efficient treatment of parasitic effects in the complete design process of microelectronic systems. In the future, no distinction between time and frequency response will exist (fT up to 110 GHz). I.e. digital, analogue design and RF design will grow together. In terms of high packing density, the different physical interferences (electronically-thermal-mechanical) have to be treated concurrently. These interferences have to be accounted for all along the design flow, starting from the early design stages, while refining the modelling and the simulation accuracy. The approach to improve EMC shall be related with other measures to improve signal-integrity (SI), robustness, functionality, power strategies, ESD, etc. to assure an integral system solution to optimally use intrinsic silicon capabilities. In the following some thoughts regarding the future development of EDA solutions which were made in the frame of the compilation of the MEDEAplus EDA Roadmap [7] are explained. It is considered the development of EDA solutions in the area Parasitic Extraction, Modeling and Analysis for the timeframe 2003 to 2008. This chapter of the MEDEAplus EDA Roadmap arose in the the years 2002/2003. In this contribution the thoughts regarding the MEDEAplus EDA Roadmap concentrate on the aspects: • EMC/SI and RF System Design with Respect to Parasitic Effects • Challenge of Packaging Technologies • Design to Noise Margin.