Modeling and Extraction of Inductances on Chip Level

The modelling and simulation of magnetic interactions on chip level has become more and more important in the last years. This is due to smaller structures and as well as rising clock frequencies. This contribution should give an overview on the analysis of parasitic inductances. It should also show their influence on the functional behaviour and the thus resulting design measures. The main problem during the extraction of parasitic on chip inductances is the fact that an inductance the function of a closed current loop. Therefore it is necessary to analyse the complete current path. It consists of signal path and current return path via the power supply system or substrate. Thus the current distribution of the whole circuit has to be known for getting correct indications on the loop inductance. Beside the geometrical structures it depends on parameters like decoupling capacitors, rise and fall times and clock frequencies. Consequently the extraction of the current path and therefore also the inductance results as a non trivial problem. Within this contribution the basic principles and mechanisms for the extraction of on chip inductances will be presented. Furthermore the dedicated inductance extraction for dynamic current analyses and the resulting design measures will be shown.