An Optimised FPGA implementation of Recursive Least Square Equalization for Fading Channels

Recursive Least Square (RLS) based equalization is a popular equalization scheme especially used in communication receivers to cater for moderate to fast time varying fading channels owing to its fast convergence. Also compared to its linear counterpart, Decision feedback equalizer (DFE) architecture works well in deep fading scenario as it does not have noise enhancement issue even if null is present in the frequency response of communication channel. The complexity of RLS scheme is significantly high which further gets increased if DFE architecture is employed. This work discusses the efficient implementation of RLS-DFE on Field Programmable Gate Arrays and its functional testing employing Hardware Co-Simulation approach. Significant reduction in hardware is achieved utilizing pipelining along with other optimizations.