A Time-Domain Multi-Channel Resistive-Sensor Interface IC With High Energy Efficiency and Wide Input Range

This paper presents a 72-channel resistive-sensor interface integrated circuit (IC). The proposed IC consists of 8 sensor oscillator units and a reference clock generator. The sensor oscillator (S-OSC) units generate pulses with pulse widths dependent on the sensor input values, and the pulses are oversampled by the reference clock using frequency dividers. The time-domain signals are fed to the time-to-digital converters (TDCs) and converted to digital values. Each S-OSC unit is time-multiplexed to measure the resistance values from 9 sensors. Multiple phases from a highly energy-efficient phase-locked loop (PLL) are used for the TDCs, resulting in a signal-to-quantization-noise ratio (SQNR) that exceeds the intrinsic signal-to-noise ratio (SNR) of the sensor oscillators. This results in an effective number of bits (ENOB) of 9.3 bits at 310 pJ per channel. The maximum ENOB that can be achieved with a division ratio (N) of 256 is 14.1 bits and can be adjusted by changing N. Using this time-domain interface approach, the IC converts the sensor resistances directly into time, extending its measurement capabilities to 10 M$\Omega$. The proposed IC, designed and fabricated in a 180-nm CMOS process with an active area of 0.015 mm${}^{2}$, consumes only 15.07 $\mu$W per channel, resulting in a channel-specific Walden figure of merit (FoM) of 0.48 pJ per conversion step. In addition, by tuning N, the IC achieves an outstanding Schreier FoM of 159.8 dB in high-resolution scenarios.