Electric-Thermal Characteristics of Bottom P-i-N Isolated Nanosheet Gate-All-Around FETs

The electrical and thermal characteristics of a novel bottom P-i-N isolation GAA NSFET has been studied. Through introducing a reverse biased p-i-n sub-TFET channel, the proposed NSFET with bottom PIN isolation scheme can reduce off leakage current to the same level as NSFET with full BDI scheme. Moreover, owing to the all silicon-based isolation instead of buried dielectric isolation in BDI scheme, the proposed bottom PIN NSFETs exhibits superior thermal properties at the same time.