Boolean Matrix Factorization Algorithm Based on Error Shaping Technique and its Application on Approximate Logic Synthesis

Boolean matrix factorization method can be used to create an approximate circuit from a given circuit. The accuracy loss of approximate circuit originates from the factorization error of each subcircuit. Hence, reducing factorization error of Boolean matrix has significant value in the approximate logic synthesis. In the case of the truth table of the logic circuit, the number of rows is much larger than the number of columns that can be utilized to further optimize the factorization method. In this brief, the error shaping technique is proposed to concentrate the factorization errors in several specific columns, which can be easily cleared by the proposed column error clear scheme. Compared with the typical factorization methods, for the truth table of an n-input, m-output logic circuit, the accuracy of proposed factorization method can be improved significantly. Finally, the proposed Boolean matrix factorization algorithm is integrated into the approximate logic synthesis tool and compared with BLASYS. The synthesis results demonstrate state-of-the-art performance.