Enhanced Multi-Bit Computation Using CIM SRAM Technology

Tackling the challenges of substantial data loading latency and excessive computational circuit area overhead prevalent in contemporary multi-bit Compute-In-Memory (CIM) SRAM macro designs, this paper introduces a strategy based on “complementary cell computation architectures coupled with complementary data inputs.” This approach establishes a high-bandwidth, high-compute-performance, and expansible multi-bit CIM SRAM macro, particularly apt for the highly parallel matrix multiplication operations encountered in neural network algorithms. The proposed CIM SRAM macro unit executes efficient binary multiplications up to 8 bits width without reliance on additional circuits such as ADC or incurring data loading delays, thereby reinforcing computational precision and system bandwidth. Simulation outcomes illustrate that, when operated at a frequency of 1GHz, the HSBC SRAM achieves an area efficiency uplift to $\mathbf{0. 556 {MB}/{mm}^{2}}$ and $\mathbf{{186TOPS/mm}^{2}}$ by expanding both input and weight data widths to 8 bits.