Automated Verification of Functional Interface Connections in Circuit Schematics

As transistor scaling approaches its physical limits, performance improvement of modern computing systems is driven by high integration and functional specialization. However, the resulting rapid growth of functional interface connections within computing systems brings challenges to verification efficiency. Current EDA tools are often inefficient at verifying these connections, requiring manual intervention to extract connection information and define verification rules. In this paper, we propose an automated verification method. Our approach designs a general schematic data structure to represent component connection information, describes processes for the automatic extraction of interface connections, and proposes a flexible rule description method to enhance extensibility. Experimental results show that our method reduces verification time from minutes to microseconds, up to 10 milliseconds, and improves the coverage of automatic schematic verification.