Design and Implementation of Hierarchical Storage Structure for MCCSIP-RAA

The Multi-core cryptographic specific instruction processor with reconfigurable accelerated array (MCCSIP-RAA) combines flexibility, efficiency, and resource utilization, but its high computational throughput also puts enormous pressure on storage structures. Based on the analysis of MCCSIP-RAA structure and multi-core processor storage system, combined with the flow processing characteristics of cryptographic data address continuity and data flow, a hierarchical storage structure combining flow storage mechanism and shared storage mechanism was designed. The first layer of the hierarchical storage structure is the input/output buffer of the MCCSIP-RAA, which adopts FIFO structure and supports burst transmission of batch data. The second layer of the hierarchical storage structure consists of input/output storage for various cryptographic specific processors, input/output storage for cryptographic acceleration arrays, and storage for related task control data. The FIFO structure is used. The third layer of the hierarchical storage structure includes internal storage of multi-core cryptographic processors, internal storage of acceleration arrays, and shared memory between processing cores, ensuring efficient processing of cryptographic calculations. A shared storage structure based on RAM was designed for subkey data with a large amount of data that is repeatedly and continuously used. A shared storage structure based on FIFO was designed for continuous and large-scale stream data processing between different cores. A separate /clustered storage structure was designed for each core, including a universal register heap, dedicated bit registers, subkey shadow registers, etc. The experimental results show that the hierarchical storage structure can effectively alleviate the contradiction between cryptographic processing flexibility, efficiency, and resource utilization in the target architecture MCCSIP-RAA. Adding smaller resources to cryptographic algorithm processing can achieve processing performance of 3–7 times for different cryptographic algorithms, effectively improving resource utilization.