Design of an Out-of-Order Superscalar Processor with Improved Register Alias Table Recovery Method

This paper implements a two-way out-of-order superscalar processor based on the RISC-V instruction set, which supports the RV32IM instruction set. The processor implements out-of-order memory execution to improve performance and uses arbitration of physical register file read ports to reduce resource consumption. Besides, this paper proposes a register alias table (RAT) recovery method based on reorder buffer marking, which can achieve rapid recovery of the RAT with a relatively low resource cost. When running CoreMark and Dhrystone, the average number of cycles the pipeline stalls due to RAT recovery is 0.056 and 0.175, respectively, significantly lower than that of the WALK algorithm. The CoreMark and Dhrystone benchmark scores for the design are 4.41 CoreMark/MHz and 2.29 DMIPS/MHz, respectively.