A Multi-Phase Clock Self-Calibrating Circuit

This paper introduces a self-calibrating circuit for multi-phase signals that enables autonomous phase offset calibration in a multi-phase delay-locked loop (MDLL). This paper refines multi-phase signals mismatches using an adjacent phase spacing error extraction technique and a high-precision phase detection circuit. The calibration algorithm addresses the static phase mismatch in the MDLL and mitigates voltage controlled delay line (VCDL) mismatches. The adjacent phase spacing difference extraction technique, by eliminating the need for an actual phase spacing quantization, the adjacent phase spacing difference extraction technique reduces the digital time converter's (DTC) required dynamic range. Utilizing a 40nm CMOS process with a core layout area of 0.02856 mm², the design simulation results demonstrate a reduction in maximum phase error from 5.96° pre-calibration to 0.718° post-calibration within an input frequency range of 1~4GHz.