Securing Silicon: A Scalable, Platform-independent Hardware Security Verification Methodology

Modern System-on-Chips (SoCs) are vulnerable due to micro architectural weakness in Register Transfer Level (RTL) implementation, having significant security risk to the sensitive design asset. Various techniques like Formal-based verification, Fuzzing and Information Flow Tracking have been proposed to accomplish the hardware security verification. Unfortunately, these techniques are not yet sufficiently developed to address the full range of potential weaknesses present in digital SoC designs. In this paper, we propose a novel and scalable hardware security verification methodology that formalize the security requirements, create use case scenarios and a comprehensive set of meaningful tests using the portable test and stimulus standard (PSS). The result shows that our proposed methodology could detect hardware weakness of the SoC design and incorporates stimuli coverage closure for quantitative assessment of test intent.