Low Power Optimization of Hybrid Logic Full Adder Design using FinFET 32nm Technology

This paper presents a low power optimisation strategy for designing a 32nm FinFET hybrid logic full adder (HLFA). The recommended architecture uses complementary metal-oxide-semiconductors (CMOS) and pass-transistor logic (PTL) to balance power consumption and performance. The optimisation reduces average power, power dissipation, latency, and PDP while maintaining acceptable area overhead. FinFET technology improves gate control and reduces leakage currents compared to CMOS technology for the HLFA. HSPICE simulation is used to evaluate the proposed design. Low power optimisation solutions including gate resizing, input capacitance reduction, and leakage current reduction are tested on average power, power dissipation, latency, and PDP. Due to the research, all of these indicators have improved, indicating that the suggested design is suitable for low-power digital system applications.