Implementation of Electronic Voting Machine in FPGA

The integration of digital technology within e-Government services has underscored the pivotal role of Electronic Voting Machines (EVMs) in enhancing public sector efficiency and citizen participation. This paper presents a systematic exploration and implementation of an EVM employing the Register Transfer Level (RTL) methodology. The research methodology encompasses a systematic analysis of the design process involving both the Ballot Unit and Control Unit of the EVM. It delineates a four-stage design process: Initial specification, RTL Description aided by Algorithmic State Machine (ASM) charts and Finite State Machine (FSM) designs, Verilog code generation, and subsequent design verification via simulation. The voting process involves registering polled votes in individual contestant registries and validating these against registries to conclude the election process. The RTL design utilizes registers, multiplexers and adders to facilitate complex circuit synthesis with multiple states. The implementation's reprogrammability and cost-efficiency highlights its viability for electoral systems ensuring transparency, security and seamless voter engagement.