Towards Readout-Aware Layout Synthesis for Spin Qubit Systems with Double Quantum Dot Readouts

A quantum compiler is required to run a quantum circuit on a quantum computer, similar to how classical compilers are required to run programs on classical computers. Spin qubits are a promising candidate for scalable quantum computers. General-purpose quantum compilers can be used for spin qubit devices, however they do not consider additional constraints imposed due to Double-Quantum-Dot (DQD) readout. For DQD readout, when a qubit in an algorithm is measured, the compiler must remap and re-route it to be adjacent to a special-purpose readout qubit, which is preserved in a known state. Moreover, this should be done in a way that minimizes overhead and maximizes the fidelity, in particular, due to noise in the readout process. This work formulates readout constraints to extend SMT (Satisfiability Modulo Theory)-based layout synthesis techniques proposed in [1] to spin qubit architectures. We define a metric, readout depth, to quantify the overheads incurred. Preliminary results, obtained from benchmarking GHZ and variational quantum eigensolver circuits on architectures with grid topologies, highlight the algorithmic tradeoffs that arise. We expect ongoing work on scaling up the methods to a larger set of algorithms will help inform the decisions of spin qubit hardware designers.