Top-Down Microarchitecture Analysis Approximation Based on Performance Counter Architecture for SiFive RISC-V Processors

Modern Out-of-Order RISC-V CPUs have complex mechanisms, making microarchitecture-level performance analysis challenging. Despite increasing Performance Monitoring Units (PMUs), interpreting this data requires deep architectural knowledge. This paper introduces a Top-down Microarchitecture Analysis (TMA) approximation to analyze application performance on RISC-V CPUs. TMA classifies performance issues into four categories by calculating metrics that reflect their proportions using predefined formulas and PMU events. We present the results of applying this method to analyze SPEC CPU2006 benchmarks on a SiFive RISC-V processor. This work is an initial step in analyzing RISC-V CPUs using TMA Level 1. The contributions of this research are threefold: (1) designing and implementing TMA for a RISC-V CPU with clear metric definitions; (2) proposing test cases and methods to verify TMA metrics and PMU implementation; (3) enabling software developers to profile workloads without requiring extensive microarchitecture knowledge.