BRISKI: A RISC-V barrel processor approach for higher throughput with less resource tax

Soft-core processors struggle to balance the tradeoffs between high instruction throughput and related area utilization. Mainstream architectures and traditional optimization approaches targeting Field-Programmable Gate Arrays (FPGA) fabrics, including pipelining, have been proven to be inefficient with more than 3 stages. In fact, the single-core instruction throughput can be enhanced at the cost of a significant increase in logic utilization which results in a poor scalability and inhibits harnessing the massive parallelism inherent to FPGAs. To address this challenge, we propose BRISKI (Barrel RISC-V for Kilo-Core Implementations), a soft-core RISC-V barrel processor design optimized for high-throughput and low-resource footprint towards Kilo-core implementations on large multi-die FPGAs. BRISKI features a barrel core architecture with an implemented configuration that is capable of interleaving 16 hardware threads (harts) on a per-cycle basis, effectively achieving a Cycles Per Instruction (CPI) rate of 1 and facilitating efficient parallel execution of instructions. BRISKI typically utilizes 789 Look-Up Tables (LUTs), with only 2 RAMB18 Block RAMs (BRAMs) instances, which provides an outstanding compute density (throughput-per-area) for resource-constrained environments and scales well in large FPGA fabrics. For example, a single core and a many-core (56-core) implementations on an Ultrascale+ VU9P FPGA demonstrate clock speeds reaching 650 MHz and 500 MHz, respectively. BRISKI scales even further to a 1,024-core/16,384-hart implementation in the same FPGA, including a PCIe backplane, while clocking at 400 MHz.