An Extended pipeline RISC-V CPU architecture

VLIW CPUs find applications in a wide range of embedded systems where high parallel computational throughput and power efficiency are essential requirements. However the relatively large registers × FUs interconnections size of VLIW architectures led to a research effort to define new variants of VLIW architectures wherein this size is reduced (closer to that of a pipeline architecture). Here, we propose to use extended-pipeline CPUs, in which multiple functional units (FUs) are arranged in consecutive pipeline stages, as opposed to the parallel arrangement of the FUs in VLIW. We show that this pipeline arrangement can obtain even better parallel computational throughput and power efficiency than an equivalent VLIW arrangement. The advantage of the extended-pipeline architecture was verified by 1) calculating the connection complexity of both architectures in a schematic model; 2) comparing an FPGA realization of a RISC-V extended-pipeline architecture to an equivalent VLIW architecture. Results (on the FPGA) show that the extended pipeline obtained better clock-latency, power, and resource utilization than the equivalent VLIW. Also, we showed that any VLIW scheduling can be turned into an equivalent extended-pipeline scheduling. Hence both architectures can obtain the same instruction level parallelism (ILP).