Improved Decimal Rounding Module based on Compound Adder

A new approach and architecture have been presented in this paper to efficiently merge the decimal rounding stage according to the IEEE 754-2008 standard based on the compound adder. This integration serves as a crucial key to improve the computation performance of both decimal floating point multiplication and fused multiply add (FMA) operation. The decimal rounding control unit is based on the IEEE 754-2008 five rounding modes. The decimal combined add/round module has been coded in the VHDL and verified using the Xilinx ISE 13.2. The overall critical path delay is compared with another design based on the BCD adder with the decimal rounding. The results have shown at least 3.4 % improvement in terms of delay reduction.