Warpage Analysis of Thermo-compression Bonding on Coreless Substrates (IMPACT 2024)

Thermo-compression bonding (TCB) technology has been used in flip chip (FC) package for high volume manufacturing especially in advanced heterogeneous integration packaging. FC package provides the advantages of lower profile, higher inputs/outputs, and higher electrical performance demanded in the high frequency/speed and great bandwidth of high-performance computing (HPC) and artificial intelligence (AI) applications. To meet these requirements, a coreless substrate is also employed in the FC package by the TCB process to achieve high electrical performance and multiple function of module, such as CoWoS (Chip-on-Wafer-on-Substrate). Similar advanced package or module like as CoWoS or FOCoS (Fan-Out Chip on Substrate) has been presented and utilized with coreless substrate in recent years. Thermal warpage issues due to mismatch of thermal expansion coefficient (CTE) in various package materials are seriously encountered. In this paper, thermal warpage analyses of a large die bonded on coreless substrate under TCB process are presented. These analyses are simulated and measured by shadow moiré. Method of improving the vacuum mechanism of the bond stage to suppress the warpage of coreless substrate is also proposed.