Extended VLIW Processor Based on RISC-V Compressed Instruction Set

RISC-V is an instruction set architecture that has attracted interest in both academic and industrial fields in recent years. RISC-V provides compressed instructions that reduce the size of each instruction. This feature contributes to the reduction of program size and is advantageous for embedded processors that have tight constraints on instruction and data memories. Therefore, implementation of compressed instructions is advantageous in terms of program size, but disadvantageous in terms of amount of hardware for embedded processors with heavy area constraints. To solve the increase amount of hardware caused by supporting compressed instructions, we propose Converting All Integer-instructions to Compressed-instructions (CAIC) method. Additionally, we propose an extended VLIW processor called RVC-VOI (RISC-V Compressed - VLIW with Overlapping Instructions) that adapts the CAIC method. The processor implements privileged instructions which are not defined in compressed instructions, without increasing the issue slot executes privileged instructions or hardware to align instruction length, by overlapping instruction fields. This paper evaluates the code size reduction rate achieved by the CAIC method and the area of RVC-VOI. The CAIC method is expected to achieve a 7.2% reduction in the code size of Quicksort and a 25.9% reduction in the code size of Dhrystone, and RVC-VOI is shown to be sufficiently small compared to Out-of-Order processors.