Design and Verification of 1×3 Router by UVM

The router is designed to manage the efficient routing of data from a single input to one of three outputs, making it a critical component in various communication systems. The architecture of the router includes essential modules such as a register, three FIFO buffers, a synchronizer, and a finite state machine (FSM). A significant enhancement in this design is the implementation of clock gating in the FSM module. This technique minimizes power dissipation by approximately 9.4% by selectively disabling the clock signal when the FSM is idle, making the design highly energy-efficient. To ensure the robustness of the design, the project undergoes extensive verification using Universal Verification Methodology. UVM enables thorough functional testing, helping to identify and correct potential issues at an early stage.