Demonstration of Robust Retention in Band Engineered FEFETs for NAND Storage Applications Using Tunnel Dielectric Layer

We perform a comprehensive study of memory retention characteristics in ferroelectric field-effect transistors with different engineered gate stacks designed to achieve a large memory window (MW) for NAND storage applications. Through this study, we show that the widely reported retention loss in these band-engineered FEFETs can be mitigated by optimizing the position of the dielectric insert. Specifically, placing the dielectric insert in the middle of the FE stack (tunnel dielectric layer, TDL) leads to excellent retention while increasing the MW to a quad-level-cell compatible level ( $\ge {7}.{5} {V}$ ). This enhanced retention is enabled by the potential wells at the TDL-FE interfaces that energetically secure the MW-enhancing charges and prevent their detrapping. In contrast, placing the dielectric insert on the gate side (gate blocking layer, GBL), while maximizing the MW, compromises retention due to the detrapping of the trapped charges at the GBL-FE interface through the GBL.