TIE Micro – Chiplets and Next-gen Packaging

As the semiconductor industry advances towards heterogeneous integrations and sophisticated Systems in Package and chiplet technologies, it becomes imperative to equip future engineers with expertise in state-of-the-art methodologies, including the application of interposers, 2.5D and 3D integration. To address this need within the roadmap of the extracurricular education for future engineers, starting in 2024, the Technologies of Interconnections in Electronics (TIE) student competition introduced a new topic - TIE Micro (TIE-$\mu$), which focuses on advanced packaging. Participants are provided with the project topics in advance and are required to submit comprehensive project design files and a detailed project report. The report must explain the student’s methodological approach, the layout design, and the results from the signal and power integrity simulations. The top ranked students present their work through an oral presentation. The jury is comprised of academia and industry representatives.