Design and Implementation of a High-Performance DSP External Memory Controller

To meet the need for rapid data transmission between the core of high-performance Digital Signal Processor (DSP) chips and external memory, as well as to manage different types of external memory flexibly, we have designed an External Memory Controller (EMC). This module not only manages multiple peripherals and supports concurrent and parallel access but also provides excellent flexibility and configurability, making it suitable for various system requirements. The EMC includes SDMA, IDMAO, IDMA1, and a dedicated ET debugging DMA channel. The SDMA channel facilitates data transfer between multiple peripherals connected to the DMA Switch Fabric outside the core and the core's internal memory spaces. The IDMA channels support fast data transfer between any two memory locations within the core. The ET dedicated DMA channel is used for JTAG debugging, ensuring the correct operation, superior performance, and reliability of the DSP chip. The EMC operates independently of CPU control, enabling rapid and large-scale data movement. After functional simulation verification and coverage analysis, the designed EMC component has achieved the expected objectives and meets the design requirements.