A $Ka$-Band Low-Phase-Noise Phase-locked Loop with Reconfigurable Output Network for Fundamental and Push-Push Modes

This paper presents a high-performance Ka-band phase-locked loop (PLL) with a reconfigurable output network, fabricated using $0.18-\mu \mathrm{m}$ CMOS technology. The oscillator core employs a series gain-stage topology and class-E load network to significantly boost output power. The reconfigurable output network incorporates two reflection-type phase shifters, which not only provide phase shifting capabilities but also serve as a mode selector, allowing the PLL to switch between fundamental and second harmonic outputs. This design achieves impressive performance metrics, featuring a minimum phase noise of -105 dBc/Hz at 1-MHz offset with an output power of 6 dBm in the frequency range of 24.2-24.6 GHz. When operating in push-push mode, the PLL delivers second-harmonic output powers exceeding -12 dBm across the entire frequency range. Compared to other reported CMOS works, this design demonstrates comparable performance and is suitable for advanced clock generations.