Design and Implementation of an Efficient Vedic Multiplier for Complex Multiplier and Complex MAC Unit in DSP Applications

In many applications of digital signal processing (DSP) and communication networks, complex multiplication is essential. The efficiency and speed of complex multiplication have a direct and important effect on the overall performance of these systems. To tackle the challenges mentioned above effectively, the present paper puts forth a proposal for a well-thought-out design and execution of a complex multiplier, integrated with its utilization in a Complex Multiply-Accumulate (Complex -MAC) module featuring various bit-sizes (8-16-32-64). These proposals are based on design improved version of Vedic multiplier (IV-VM) and involves the utilization of a hybrid adder that combines an enhanced Han Carlson adder with a carry-select adder (HHC-CSLA). This hybrid adder is employed to carry out addition operations for complex multiplier, and partial products in the Vedic multiplier VM, as well as for computing the sum of products within the complex MAC unit. Using the Xilinx ISE14.7 tool and VHDL language, the suggested designs are generated in several Field-Programmable Gate Array (FPGA) families. All designs have shown significant reductions in latency and space utilization across all devices in terms of performance.