A New Interface for Power Hardware-in-the-Loop Simulation Using Nelder-Mead Algorithm

A cyber-physical system is a system that integrates computation and physical processes. Such a system has found numerous applications in power systems. One such application is power hardware-in-the-loop (PHIL) simulation. In the context of PHIL simulation, a hardware device under test (DUT) is typically linked to a digital real-time simulator (DRTS) via a PHIL interface. Over time, several PHIL interfaces have been proposed and explored. Notably, the ideal transformer model (ITM) stands out due to its popularity, primarily for its ease of implementation. Other PHIL interfaces, such as partial circuit duplication (PCD) and damping impedance, can be viewed as extensions of the ITM concept. These PHIL interfaces necessitate a strict impedance ratio between the physical (i.e., the DUT) and the cyber parts (i.e., the system modeled in DRTS) before embarking on a PHIL implementation. This prerequisite can often prove to be a demanding and complex task. This article introduces a novel PHIL interface for PHIL using Nelder–Mead (NM) algorithm, designed to eliminate such constraints. Notably, the proposed PHIL interface offers an expanded stability region when compared with ITM, thus rendering it suitable for a broader range of PHIL applications. The effectiveness of this proposed method has been confirmed by a practical PHIL setup.